1. Field of the Invention
The present invention relates to a video signal processing apparatus. More particularly, the present invention relates to generate both progressive and interlace video signals of the video signal processing apparatus.
2. Description of the Prior Art
Video displaying is usually achieved by continuously displaying the consecutive still video pictures or video images, which are then captured by human eyes to render a dynamic or a motion effect. Each video picture/image includes several scanning lines starting from the upper-left corner of the video picture/image. Take the well-known NTSC standard for an example, the format type for a video picture/image in the NTSC standard includes 525 scanning lines, among which approximately 480 scanning lines are effective, or so called effective scanning lines.
When a video display apparatus, like a TV, a projector or a monitor, is employed for video displaying, there are generally two kinds of scanning methods: interlace scanning method (interlace scan), and progressive scanning method (progressive scan). The interlace scanning method has been developed for a long time and is used more often. Most of the TV in the current market utilize interlace scanning method for video displaying. However, there is an increasing demand for progressive scanning. Therefore, some of the video display apparatuses are also designed to utilize progressive scanning.
Most well-known format types for video displaying include: interlaced video (480i) of 525 total scanning lines and 480 effective scanning lines, interlaced video (1080i) of 1125 total scanning lines and 1080 effective scanning lines, progressive video (480p) of 525 total scanning lines and 480 effective scanning lines, and progressive video (720p) of 750 total scanning lines and 720 effective scanning lines.
In the interlace scanning method, the odd numbers of scanning lines, i.e. the first, the third, the fifth . . . , are first scanned. Usually it is also called the first field or “odd field”. Then, the even numbers of scanning lines go on, i.e. the second, the fourth, the sixth, the eighth . . . . Usually it is also called the second field or “even field”. Thus, the smooth video displaying is in fact formed by controlling the scanning lines to be displayed on the video display apparatus in a first-odd-and-then-even way, or in an odd-and-even alternative way.
As for the progressive scanning method, the scanning lines are displayed sequentially, i.e. the first, the second, the third, the fourth . . . to the end. They constitute so-called a “frame”, and the rendered pictures are usually more refined and subtler. The scanning speed is thus twice as that of the interlace scanning method because the progressive scanning method displays twice the scanning lines in the same time period. The data amount for the progressive scan is also twice as much as that for the interlace scan.
FIG. 1 is a block diagram of video signal processing apparatus 10 according to the prior art. The video signal processing apparatus 10 is generally designed in a single chip. The video signal processing apparatus 10 of the prior art processes the video signals 22 transmitted from an external video memory 20 to output interlace video signals 11 that can be displayed by a video display apparatus. The video signal processing apparatus 10 comprises an interlace format picture processor 12 and a TV encoder 14. The interlace format picture processor 12 reads the video signals 22, transmitted from the video memory 20, in compliance with the interlace scanning method, and then it further transmits the signals into the TV encoder 14 to perform low-pass filtering and to adjust chrominance, brightness and contrast. The interlace format signals are then encoded into interlace signals 11 that are in compliance with the video standard of the video display apparatus.
FIG. 2 is a schematic diagram in which the interlace video signal 11 in FIG. 1 is transformed into a progressive video signal 31. If the progressive video display apparatus is to perform video displaying in a progressive scanning way, the inputted video signals have to be the corresponding progressive video signal 31. In the prior art, the video signal processing apparatus 10 utilizes an external interlace-to-progressive transforming IC circuit 13 to transform the interlace video signal 11 into the progressive video signal 31. More specifically, the signal transformation is performed by inserting a scanning line, either by means of interpolation or simulation, between two consecutive scanning lines of the interlace video signals 11. In this way, the interlace field signals can be interpolated or simulated as the progressive frame signal, and the interlace video signals 11 can therefore be transformed into the progressive video signal 31. Because the interlace-to-progressive transforming IC circuit 13 needs to be designed on another chip outside the video signal processing apparatus 10, the production cost is consequently increased. The aforementioned method is restricted by cost in practical application.
FIG. 3 is a block diagram of the prior art video signal processing apparatus 30 for generating a progressive video signal 31. The video signal processing apparatus 30 of the prior art, designed on a single chip, is used for generating progressive video signals 31.
This video signal processing apparatus 30 has the same function as the video signal processing apparatus 10. Furthermore, it processes the video signals 22 in compliance with the progressive scanning method. Because the picture processor 32 has the built-in functions of interpolation and/or simulation, after reading the video signals 22, it generates the corresponding frame signals in compliance with the progressive scanning method. Besides, the TV encoder 34 can encode the signals, which come from the picture processor 32, to be the progressive video signals 31 in compliance with the video standard of the video display apparatus.
FIG. 4 is a block diagram in which the video signal processing apparatus 30 of FIG. 3 generates interlace video signals 11. It is worthy to mention that the video signal processing apparatus 30, with the same function as the video signal processing apparatus 10, can output the interlace video signals 11 on its own or independently. When the video signal processing apparatus 30 is used for generating the interlace video signals 11, the picture processor 32, using the same way as the picture processor 12 of FIG. 1, reads the video signals 22 by disabling or without using the function of interpolation and/or simulation. That is, the picture processor 32 of the video signal processing apparatus 30 has two modes, the progressive mode/format and the interlace mode/format. Therefore, the video signal processing apparatus 30, depending on different situations, alternatively outputs progressive video signals 31 or interlace video signals 11.
Comparing the embodiment of the video signal processing apparatus 30 of FIG. 3 and FIG. 4 with the embodiment of the video signal processing apparatus 10 of FIG. 2, the video signal processing apparatus 30 generates the progressive video signal 31 without utilizing the external interlace-to-progressive transforming IC circuit 13, so the cost of production can be reduced. However, the video signal processing apparatus 30 can only display the progressive video signal 31 or the interlace video signal 11 alternatively, but not both together.